This invention relates to chip clock distribution circuits and particularly to a constant delay clock buffer therefor with voltage compensation.
Trademarks: S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
The delay in distributing a clock to all parts of a chip is becoming a larger fraction of clock cycle time as chip frequency increases. Thus, in future CMOS chips even small delay variations in the branches of the clock distribution tree will result in large clock skew and/or large clock jitter. The delay of prior art clock distribution buffer circuits varied with voltage. When the local voltage powering the buffer is reduced (local rail collapse), the delay through the prior art buffer circuit increases. Multiple clock distribution buffer circuits are spatially distributed to generate and distribute a synchronous clock to all parts of a chip. In general the local Vdd and ground voltages powering each of these buffers is different and this results in a skewed clock arrival between different parts of the chip It is not always possible to eliminate the spatial variation in voltage which arises when the current demands of various parts of the chip quickly change (dI/dt). Thus, it would be beneficial to develop a clock buffer circuit with a constant delay independent of local Vdd and ground voltages. Known prior art clock distribution buffers have no voltage compensation, and the voltage compensated clock buffer invention illustrated herein results in a significant reduction in clock skew.
In accordance with the invention a voltage-compensating (constant delay) clock buffer circuit for a chip clock distribution circuit provides a constant delay independent of local Vdd and ground voltages by employing a voltage-compensating constant delay clock buffer circuit having an input, an output, a first voltage rail, a second voltage rail, a first inverter stage, a second inverter stage, and a control circuit to adjust the delay of said first inverter stage, said control circuit responsive to said first voltage rail and said second voltage rail to provide dynamic control of the delay through the first inverter stage.
The preferred embodiment of the invention is further implemented with detail which provides a primary reference Vdd and primary reference ground which are distributed to each clock buffer of the clock distribution network. These references do not suffer from dI/dt induced rail collapse and voltage rail overshoot since they are only supplied to clock buffer circuits and draw very little current (just enough to incrementally speed up first clock buffer stage in response to local rail collapse.) The gain of this first stage is controlled by a circuit which generates a control voltage approx. one device threshold voltage below the local Vdd and a control voltage approx. one device threshold voltage above the local ground. These control voltages effect the operation of supplemental device stacks in series with the first stage of the clock buffer. As local Vdd collapses below the reference Vdd, the supplemental PFET device stack assists the pull-up of the first stage; thereby reducing the delay through the first stage. Similarly as local ground rises above the reference ground, the supplemental NFET device stack assists the pulldown of the first stage; thereby reducing the delay through the first stage. The circuit which creates the control voltages dissipated a small amount of DC current. The invention includes a control pin which can be used to eliminate this DC current during tests which are rendered ineffective in the presence of such currents.